[]=============================================[] [] JUEGO DE INSTRUCCIONES DEL 80x86/x87 [] []=============================================[] Sintaxis Ejemplo -------- ------- ASCII Adjust after Addition AAA aaa ASCII Adjust before Division AAD aad ASCII Adjust after Multiply AAM aam ASCII Adjust after Subtraction AAS aas Add with Carry ADC reg,reg adc dx,cx ADC mem,reg adc WORD PTR m16[2],dx ADC reg,mem adc dx,DWORD PTR m32[2] Add ADD reg,reg add ax,bx ADD mem,reg add total, cx ADD reg,mem add cx,incr ADD reg,immed add bx,6 ADD mem,immed add pointers[bx][si],6 ADD accum,immed add ax,10 Logical AND AND reg,reg and dx,bx AND mem,reg and bitmask,bx AND reg,mem and bx,masker AND reg,immed and dx,0F7h AND mem,immed and masker,100lb AND accum,immed and ax,0B6h Adjust Requested Privilege Level ARPL reg,reg arpl ax,cx ARPL mem,reg arpl selector,dx Check Array Bounds BOUND reg16,mem32 bound di,base-4 BOUND reg32,mem64 bound di,base-4 Bit Scan Fordward BSF reg16,reg16 bsf cx,bx BSF reg32,reg32 bsf cx,bx BSF reg16,mem16 bsf ecx,bitmask BSF reg32,mem32 bsf ecx,bitmask Bit Scan Reverse BSR reg16,reg16 bsr cx,dx BSR reg32,reg32 bsr cx,dx BSR reg16,mem16 bsr eax,bitmask BSR reg32,mem32 bsr eax,bitmask Byte Swap BSWAP reg32 bswap ebx Bit Tests BT reg16,immed8* bt ax,4 BT mem16,immed8* bt [bx],4 BT reg16,reg16* bt ax,bx BT mem16,reg16* bt [bx],dx BTC reg16,immed8* btc edi,4 BTC mem16,immed8* btc color[di],4 BTC reg16,reg16* btc eax,ebx BTC mem16,reg16* btc [bp+8],si BTR reg16,immed8* btr bx,17 BTR mem16,immed8* btr [bx],27 BTR reg16,reg16* btr cx,di BTR mem16,reg16* btr rotate,cx BTS reg16,immed8* bts ax,4 BTS mem16,immed8* bts maskit,4 BTS reg16,reg16* bts bx,ax BTS mem16,reg16* bts flags[bx],cx * Operandos tambi‚n pueden ser de 32 bits Call Procedure CALL label call upcase call distant CALL reg call ax CALL mem32 call [bx] CALL mem32 call DWORD PTR [bx] Convert Data CBW cbw CWD cwd CWDE cwde CDQ cdq Modify Carry Flag CLC clc STC stc CMC cmc Clear or Set Direction Flag CLD cld STD std Clear or Set Interrupt Flag CLI cli STI sti Clear Task-Switched Flag CLTS clts Compare Two Operands CMP reg,reg cmp dl,cl CMP mem,reg cmp array[si],bl CMP reg,mem cmp bh,array[si] CMP reg,immed cmp bx,24 CMP mem,immed cmp tester,4000 CMP accum,immed cmp ax,1000 Compare String CMPS [segreg:] src,[ES:] dest cmps source,es:dest CMPSB [[segreg:[src,]ES:] dest] cmpsb CMPSW [[segreg:[src,]ES:] dest] cmpsw CMPSD [[segreg:[src,]ES:] dest] cmpsd Compare and Exchange CMPXCHG mem,reg cmpxchg string,bl CMPXCHG reg,reg cmpxchg bx,cx CMPXCHG8B reg,mem64 cmpxchg8b ax,[bx] CPUID cpuid Decimal Adjust after Addition DAA daa Decimal Adjust after Subtraction DAS das Decrement DEC reg dec ax DEC mem dec counter Unsigned Divide DIV reg div cx DIV mem div [bx] Make or Destroy Stack Frame ENTER immed16,0 enter 4,0 ENTER immed16,1 enter 0,1 ENTER immed16,immed8 enter 6,4 LEAVE leave Calculate 2(^X)-1 F2XM1 fm2xi Absolute Value FABS fabs Add FADD [reg,reg] fadd FADD memreal fadd shortreal FADDP reg,ST faddp st(6),st FIADD memint fiadd int16 Load FBLD membcd fbld packbck FILD memint fild quads[si] FLD reg fld st(3) FLD mem32real fld longreal FLD mem64real FLD mem80real Store FBSTP membcd fbstp bcds[bx] FIST memint fist doubles[8] FISTP memint fistp longint FST reg fst st FST memreal fst longs[bx] FSTP reg fstp st(3) FSTP mem32real fstp longreal FSTP mem64real FSTP mem80real Change Sign FCHS fchs Clear Exceptions FCLEX fclex FNCLEX fnclex Compare FCOM fcom FCOMP fcomp FCOMPP fcompp FICOM memint ficom double FICOMP memint ficomp darray[di] Sine/Cosine FSIN fsin FCOS fcos FSINCOS fsincos Increment or Decrement Stack Pointer FINCSTP fincstp FDECSTP fdecstp Divide FDIV [reg,reg] fdiv st(5),st FDIV memreal fdiv longreal FDIVP reg,ST fdivp st(6),st FIDIV memint didiv warray[di] Divide Reversed FDIVR [reg,reg] fdivr st(5),st FDIVR memreal fdivr longreal FDIVRP reg,ST fdivrp st(6),st FIDIVR memint didivr warray[di] Free Register FFREE ST(i) ffree st(3) Initialize Coprocessor FINIT finit FNINIT fninit Load Constant FLD1 fld1 ; (+1.0) FLDZ fldz ; (+0.0) FLDPI fldpi ; (pi) FLDL2E fldl2e ; (Log (e)) ; 2 FLDL2T fldl2t ; (Log (10)) ; 2 FLDLG2 fldlg2 ; (Log (2)) ; 10 FLDLN2 fldln2 ; (Log (2)) ; e Load or Store Control Word FLDCW mem16 fldcw ctrlword FSTCW mem16 fstcw ctrlword FNSTCW mem16 fnstcw ctrlword Load or Store Environment State FLDENV mem fldenv [bp+10] FSTENV mem fstenv [bp-14] FNSTENV mem fnstenv [bp-14] Multiply FMUL [reg,reg] fmul st(5),st FMULP reg,ST fmulp st(6),st FIMUL memint fimul warray[di] No Operation FNOP fnop Partial Arctangent and Tangent FPATAN fpatan FPTAN fptan Partial Remainder FPREM fprem FPREM1 fprem1 Round to Integer FRNDINT frndint Save or Restore Coprocessor State FRSTOR mem frstor [bp-94] FSAVE mem fsave [bp-94] FNSAVE mem fnsave [bp-94] Scale FSCALE fscale Square Root FSQRT fsqrt Store Status Word FSTSW mem16 fstsw statword FSTSW AX fstsw ax FNSTSW mem16 fnstsw statword FNSTSW AX fnstsw ax Subtract FSUB [reg,reg] fsub st,st(2) FSUB memreal fsub longreal FSUBP reg,ST fsubp st(6),st FISUB memint fisub double Subtract Reversed FSUBR [reg,reg] fsubr st,st(2) FSUBR memreal fsubr longreal FSUBRP reg,ST fsubrp st(6),st FISUBR memint fisubr double Test for Zero FTST ftst Unordered Compare FUCOM [reg] fucom st(2) FUCOMP [reg] fucomp st(7) FUCOMPP fucompp Wait FWAIT fwait Examine FXAM fxam Exchange Registers FXCH [reg] fxchg st(3) Extract Exponent and Significand FXTRACT fxtract Y log(sub2)(X) FYL2X fyl2x Y log(sub2)(X+1) FYL2XP1 fyl2xp1 Halt HLT hlt Signed Divide IDIV reg idiv dl IDIV mem idiv itemp Signed Multiply IMUL reg imul dx IMUL mem imul factor IMUL reg,immed imul cx,25 IMUL reg,reg,immed imul dx,ax,18 IMUL reg,mem,immed imul bx,[si],60 IMUL reg,reg imul cx,ax IMUL reg,mem imul dx,[si] Input from Port IN accum,immed in ax,60h IN accum,DX in ax,dx Increment INC reg inc bx INC mem inc vpage Input from Port to String INS [ES:]dest, DX ins es:instr,dx INSB insb INSW insw INSD insd Interrupt INT immed8 int 25h INT 3 int 3 INTO into Invalidate Data Cache INVD invd Invalidate TLB Entry INVLPG invlpg es:entry Interrupt Return IRET iret IRETD iretd IRETF iretf IRETDF iretdf (* Real or V86 mode.*) Jump Conditionally (Jcondition label) JB/JNAE CF=1 Jump if below/not above or equal (unsigned comparisons) JAE/JNB CF=0 Jump if above or equal/not below (unsigned comparisons) JBE/JNA CF=1 or ZF=1 Jump if below or equal/not above (unsigned comparisons) JA/JNBE CF=0 and ZF=0 Jump if above/not below or equal (unsigned comparisons) JE/JZ ZF=1 Jump if equal (zero) JNE/JNZ ZF=0 Jump if not equal (not zero) JL/JNGE SF<>OF Jump if less/not greater or equal (signed comparisons) JGE/JNL SF=OF Jump if greater or equal/not less (signed comparisons) JLE/JNG ZF=1 or SF<>OF Jump if less or equal/not greater (signed comparisons) JG/JNLE ZF=0 and SF=OF Jump if greater/not less or equal (signed comparisons) JS SF=1 Jump if sign JNS SF=0 Jump if not sign JC CF=1 Jump if carry JNC CF=0 Jump if not carry JO OF=1 Jump if overflow JNO OF=0 Jump if not overflow JP/JPE PF=1 Jump if parity/parity even JNP/JPO PF=0 Jump if no parity/parity odd Jump if CX is Zero JCXZ label jcxz not_found JECXZ label Jump Unconditionally JMP label jmp NEAR PTR distant jmp distant JMP reg16 jmp ax JMP mem16 jmp table[di] JMP reg32 jmp eax JMP mem32 jmp fpointer[si] JMP mem48 jmp FWORD PTR [di] Transfer between Flags and AH LAHF lahf SAHF sahf Load Access Rights LAR reg,reg lar ax,bx LAR reg,mem lar cx,selector Load Far Pointer LDS reg,mem lds si,fpointer LES reg,mem les di,fpointer LFS reg,mem lfs edi,fpointer LGS reg,mem lgs bx,fpointer LSS reg,mem lss bp, fpointer Load Effective Address LEA reg,mem lea bx,npointer Load Descriptor Table LGDT mem48 lgdt descriptor LIDT mem48 lidt descriptor LLDT reg16 lldt ax LLDT mem16 lldt selector Load or Store Machine Status Word LMSW reg16 lmsw ax LMSW mem16 lmsw machine SMSW reg16 smsw ax SMSW mem16 smsw machine Lock the Bus LOCK lock Load String Operand LODS [segreg:]src lods es:source LODSB [[segreg:]src] lodsb LODSW [[segreg:]src] lodsw LODSD [[segreg:]src] lodsd Loop/Loop if LOOP label loop wend LOOPE label loope again LOOPEW label LOOPED label LOOPZ label loopz again LOOPZW label LOOPZD label LOOPNE label loopne for_next LOOPNEW label LOOPNED label LOOPNZ label loopnz for_next LOOPNZW label LOOPNZD label Load Segment Limit LSL reg,reg lsl ax,bx LSL reg,mem lsl cx,seg_lim Load or Store Task Register LTR reg16 ltr ax LTR mem16 ltr task STR reg16 str cx STR mem16 str taskreg Move Data / Move to/from Special Registers MOV reg,reg mov bp,sp MOV mem,reg mov array[di],bx MOV reg,mem mov bx,pointer MOV mem,immed mov [bx],15 MOV reg,immed mov cx,256 MOV mem,accum mov total,ax MOV accum,mem mov al,string MOV segreg,reg16 mov ds,ax MOV segreg,mem16 mov es,psp MOV reg16,segreg mov ax,ds MOV mem16,segreg mov stack_save,ss MOV reg32,controlreg mov eax,cr0 mov eax,cr2 mov eax,cr3 mov eax,cr4 MOV controlreg,reg32 mov cr0,eax MOV reg32,debugreg mov edx,dr0 MOV debugreg,reg32 mov dr0,ecx Move String Data MOVS [ES:]dest,[segreg:]src movs dest,es:source MOVSB [[ES:]dest,[segreg:]src] movsb MOVSW [[ES:]dest,[segreg:]src] movsw MOVSD [[ES:]dest,[segreg:]src] movsd Move with Sign- or Zero-Extend MOVSX reg,reg movsx bx,al MOVSX reg,mem movsx eax,bsign MOVZX reg,reg movzx bx,al MOVZX reg,mem movzx eax,bunsign Unsigned Multiply MUL reg mul bx MUL mem mul WORD PTR [bx] Two's-Complement Negation NEG reg neg ax NEG mem neg balance No Operation NOP nop One's-Complement Negation NOT reg not ax NOT mem not masker Logical OR OR reg,reg or ax,dx OR mem,reg or bits,dx OR reg,mem or dx,color[di] OR reg,immed or dx,110110b OR mem,immed or flag_rec,8 OR accum,immed or ax,40h Output to Port OUT immed8,accum out 60h,al OUT DX,accum out dx,ax Output String to Port OUTS DX,[segreg:]src outs dx,buffer OUTSB [DX,[segreg:]src] outsb OUTSW [DX,[segreg:]src] outsw OUTSD [DX,[segreg:]src] outsd Pop / Push / Pop or Push All POP reg pop cx POP mem pop param POP segreg pop es PUSH reg push dx PUSH mem push [di] PUSH segreg push es PUSH immed push 15000 POPA popa POPAD popad PUSHA pusha PUSHAD pushad Push or Pop Flags POPF popf POPFD popfd PUSHF pushf PUSHFD pushfd Rotate RCL reg,1 rcl dx,1 RCL mem,1 rcl WORD PTR [si],1 RCL reg,CL rcl dx,cl RCL mem,CL rcl masker,cl RCL reg,immed8 rcl bx,5 RCL mem,immed8 rcl WORD PTR [bp+8],3 RCR reg,1 rcr bl,1 RCR mem,1 rcr WORD PTR m32[0],1 RCR reg,CL rcr bl,cl RCR mem,CL rcl WORD PTR [bx=di],cl RCR reg,immed8 rcr si,9 RCR mem,immed8 rcr masker,3 ROL reg,1 rol ax,1 ROL mem,1 rol bits,1 ROL reg,CL rol ax,cl ROL mem,CL rol color,cl ROL reg,immed8 rol ax,13 ROL mem,immed8 rol BYTE PTR [bx],10 ROR reg,1 ror ax,1 ROR mem,1 ror WORD PTR [bx],1 ROR reg,CL ror dx,cl ROR mem,CL ror color,cl ROR reg,immed8 ror bl,3 ROR mem,immed8 ror bits,6 RDMSR rdmsr Repeat String / Repeat String Conditionally REP INS dest,DX rep ins dest,dx REP MOVS dest,src rep movs dest,source REP OUTS DX,src rep outs dx,source REP LODS dest rep lods dest REP STOS dest rep stos dest REPE CMPS src,dest repe cmps src,dest REPE SCAS dest repe scas dest REPNE CMPS src,dest repne cmps src,dest REPNE SCAS dest repne scas dest Return from Procedure RETN retn RETN immed16 retn 8 RETF retf RETF immed16 retf 32 RSM rsm Shift SAL reg,1 sal bx,1 SAL mem,1 sal WORD PTR m32[0],1 SAL reg,CL sal ah,cl SAL mem,CL sal BYTE PTR [di],cl SAL reg,immed sal cx,6 SAL mem,immed sal array[bx+di],14 SAR reg,1 sar di,1 SAR mem,1 sar count,1 SAR reg,CL sar bx,cl SAR mem,CL sar sign,cl SAR reg,immed sar bx,5 SAR mem,immed sar sign_count,3 SHL reg,1 shl si,1 SHL mem,1 shl index,1 SHL reg,CL shl di,cl SHL mem,CL shl index,cl SHL reg,immed shl di,2 SHL mem,immed shl unsign,4 SHR reg,1 shr dh,1 SHR mem,1 shr unsign[di],1 SHR reg,CL shr dx,cl SHR mem,CL shr WORD PTR m32[2],cl SHR reg,immed shr bx,8 SHR mem,immed shr mem16,11 Subtract with Borrow SBB accum,immed sbb ax,320 SBB reg,immed sbb dx,45 SBB mem,immed sbb WORD PTR m32[2],40 SBB reg,reg sbb dx,cx SBB mem,reg sbb WORD PTR m32[2],dx SBB reg,mem sbb dx,WORD PTR m32[2] Scan String Flags SCAS [ES]dest scas es:destin SCASB scasb SCASW scasw SCASD scasd Set Conditionally SETcondition reg8 setc dh SETcondition mem8 setle flag Store Descriptor Table SGDT mem48 sgdt descriptor SIDT mem48 sidt descriptor SLDT reg16 sldt ax SLDT mem16 sldt selector Double-Precision Shift SHLD reg16,reg16,immed8 shld ax,dx,10 SHLD reg32,reg32,immed8 SHLD mem16,reg16,immed8 shld bits,cx,5 SHLD mem32,reg32,immed8 SHLD reg16,reg16,CL shld ax,dx,cl SHLD reg32,reg32,CL SHLD mem16,reg16,CL shld masker,ax,cl SHLD mem32,reg32,CL SHRD reg16,reg16,immed8 shrd cx,si,3 SHRD reg32,reg32,immed8 SHRD mem16,reg16,immed8 shrd [di],dx,5 SHRD mem32,reg32,immed8 SHRD reg16,reg16,CL shrd ax,dx,cl SHRD reg32,reg32,CL SHRD mem16,reg16,CL shrd [bx],ax,cl SHRD mem32,reg32,CL Store String Data STOS [ES:]dest stor es:dstring STOSB [[ES:]dest] stosb STOSW [[ES:]dest] stosw STOSD [[ES:]dest] stosd Subtract SUB reg,reg sub ax,bx SUB mem,reg sub array[di],bi SUB reg,mem sub al,[bx] SUB reg,immed sub bl,7 SUB mem,immed sub total,4000 SUB accum,immed sub ax,32000 Logical Compare TEST reg,reg test dx,bx TEST mem,reg test flags,dx TEST reg,immed test cx,30h TEST mem,immed test masker,1 TEST accum,immed test ax,90h Verify Read or Write VERR reg16 verr ax VERR mem16 verr selector VERW reg16 verw cx VERW mem16 verw selector Wait WAIT wait Invalidate Data Cache WBINVD wbinvd WRMSR wrmsr Exchange and Add XADD reg,reg xadd dl,al XADD mem,reg xadd string,bl Exchange XCHG reg,reg xchg cx,dx XCHG reg,mem xchg bx,pointer XCHG mem,reg xchg [bx],ax XCHG accum,reg xchg ax,cx XCHG reg,accum xchg cx,ax Translate XLAT [[segreg:]mem] xlat XLATB [[segreg:]mem] xlatb es:table Exclusive OR XOR reg,reg xor cx,bx XOR reg,mem xor cx,flags XOR mem,reg xor [bp+10],cx XOR reg,immed xor bl,1 XOR mem,immed xor switches[bx],101b XOR accum,immed xor ax,01010101b